The present invention relates to integrated circuits and, more particularly, to a temperature sensor circuit.
Many systems-on-chips (SoCs) require elaborate thermal management, and so integrated or on-die temperature sensors are implemented to measure die temperatures. Using the temperature value provided by the temperature sensor, many decisions can be performed such as increasing or decreasing the operating frequency and/or voltage and gracefully shutting down the SoC if the temperature exceeds a predetermined reliability limit in order to prevent critical failures of the system.
The accuracy of an on-die temperature sensor is defined as the difference between the actual die temperature and the temperature sensor measurement. The smaller the measurement error, the higher the accuracy of the sensor.
A typical on-die temperature sensor may include (i) a PTAT (proportional to absolute temperature) generator that generates an analog PTAT voltage that ideally is linearly proportional to temperature and (ii) an analog-to-digital (A/D) converter that converts the analog PTAT voltage level to a digital value that can be converted to temperature based on a predetermined mapping stored in memory in a look-up table (LUT).
FIG. 1 is a schematic circuit diagram of a conventional PTAT generator 100. As shown in FIG. 1, the PTAT generator 100 has an operational amplifier (opamp) A whose two (positive and negative) inputs are generated by two current-mirrored legs configured in a negative-feedback arrangement. The first leg comprises a first PMOS (p-type metal oxide semiconductor) transistor MP1 in series with a first pnp-type bipolar transistor device Q1, and the second leg comprises a second PMOS transistor MP2 in series with a first resistor R1 and a second pnp-type bipolar transistor device Q2, which is m times larger than the device Q1, where m>1. Note that the transistors MP1 and MP2 are (ideally) the same size, such that the currents flowing through the first and second legs will be (ideally) the same.
As a result of the negative-feedback arrangement in the PTAT generator 100, the voltages at the two inputs to the opamp A will be driven to the same level. Since the bases of the pnp devices Q1 and Q2 are tied together to ground (Vss), and since Q2 is m times larger than Q1, the emitter voltage of Q2 will be lower than the emitter voltage of Q1. Since the voltage level at the opamp's negative input is equal to the Q1 emitter voltage, and since the voltage level at the opamp's positive input is driven to that same Q1 emitter voltage level, the voltage across resistor R1 will be equal to the difference between the Q1 and Q2 emitter voltage levels, which is equal to the base-to-emitter voltage difference ΔVBE between Q1 and Q2.
For equal levels of current flow, the base-to-emitter voltage difference ΔVBE between Q1 and Q2 is given by Equation (1) as follows:ΔVBE=VT*ln(m)  (1)where VT is the voltage equivalent of temperature given by Equation (2) as follows:VT=k*T/q,  (2)where k is the Boltzmann constant, T is temperature in degrees Kelvin, and q is the fundamental charge constant.
As shown in FIG. 1, the PTAT generator 100 also comprises a third, current-mirrored leg comprising a third PMOS transistor MP3 in series with a second resistor R2, where the size of MP3 is (ideally) identical to the sizes of MP1 and MP2, such that the current flowing through the third leg is (ideally) identical to the currents flowing through the first and second legs, and where the resistances of R1 and R2 may be (but do not have to be) different. As such, the PTAT voltage Vptat presented at the output of the PTAT generator 100 is given by Equation (3) as follows:Vptat=(R2*ΔVBE)/R1=(R2*VT*ln(H))/R1=(R2*k*T*ln(m))/(R1*q)  (3)where R1 and R2 are the respective resistances of the resistors R1 and R2. In other words, according to equation (3), the PTAT voltage Vptat generated by PTAT generator 100 of FIG. 1 is (ideally) a linear function of the temperature T and a constant. Note that, although the resistance levels R1 and R2 may vary with temperature, their ratio R2/R1 should be substantially constant with temperature and process variation.
In an ideal implementation, the sizes of the three PMOS devices MP1, MP2, and MP3 are exactly equal. In a real-world implementation, however, there will be random transistor mismatches (such as random variations in transistor width, length, threshold voltages, mobility, etc.) that result in differences between the current levels in the three legs and an offset at the input to the opamp A, all of which will result in non-linearity in the response of the PTAT generator 100 to changes in temperature. As such, in order for an on-die temperature sensor employing the PTAT generator 100 of FIG. 1 to operate with sufficient precision for some SoC applications, the operations of the PTAT generator 100 need to be calibrated during factory testing (also referred to as trimming) at multiple different temperature levels, e.g., at high temperature (e.g., 125 C), at low temperature (e.g., −40 C), and again at room temperature (e.g., 25 C) in order to generate the LUT used to map the A/D converter output levels to temperature. This requirement for multi-temperature trimming increases the test time and cost.
Another disadvantage of conventional on-die temperature sensors is the need to implement an A/D converter, which can also increase the cost of the SoC.